FPGA IMPLEMENTATION OF MODIFIED CANNY EDGE DETECTOR

FPGA IMPLEMENTATION OF MODIFIED CANNY EDGE DETECTOR

 

ABSTRACT

 

EDGE detectors have been an essential part of many computer vision systems. The edge detection process serves to simplify the analysis of images by drastically reducing the amount of data to be processed, while at the same time preserving useful structural information about object boundaries. There is certainly a great deal of diversity in the applications of edge detection, but it is felt that many applications share a common set of requirements. This paper proposes a distributed Canny edge detection algorithm which can be mapped onto multi-core architectures for high throughput applications. In contrast to the conventional Canny edge detection algorithm which makes use of the global image gradient histogram to determine the threshold for edge detection, the proposed algorithm adaptively computes the edge detection threshold based on the local distribution of the gradients in the considered image as blocks. This will results in significantly reduced memory requirements, decreased latency and increased throughput with no loss in edge detection performance as compared to the original Canny algorithm. An FPGA-based hardware architecture of our proposed algorithm is presented in this paper. Simulation results are presented to illustrate the performance of the proposed distributed Canny edge detector. The FPGA simulation results show that we can process a 512×512 image in 0.227ms at a clock rate of 100 MHz.

 

Index Terms— Canny Edge detector, Distributed Processing,Non-uniform quantization, FPGA