POWER REDUCTION IN SCAN BASEDBIJT USING BS-LFSR AND SCAN-CHAIN ORDING

POWER REDUCTION IN SCAN BASEDBIJT USING BS-LFSR AND SCAN-CHAIN ORDING

 

                                                              
                                                          

Abstract:  The design for low power has become one of the greatest challenges in high-performance very large scale integration (VLSI) design. It has been found that the power consumed during test mode operation is often much higher than during normal mode operation. This is because most of the consumed power results from the switching activity in the nodes of the circuit under test (CUT), BIST technique uses linear feedback shift register (LFSR) for generating test pattern. The proposed design, called bit-swapping LFSR (BS-LFSR), is composed of an LFSR and a 2 × 1 multiplexer. When used to generate test patterns for scan-based built-in self-tests, it reduces the number of transitions that occur at the scan-chain input during scan shift operation by 50% when compared to those patterns produced by a conventional LFSR. Hence, it reduces the overall switching activity in the circuit under test during test applications. These techniques have a substantial effect on average- and peak-power reductions with negligible effect on fault coverage or test application time.

Keywords: Built-in self-test (BIST), linear feedback shift register (LFSR), lowpower test, pseudorandom pattern generator, scan-chain ordering, weighted switching activity (WSA).